1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit and, more particularly, to apparatus and methods for effectively supplying a power source to input buffers in a semiconductor integrated circuit.
2. Related Art
Generally, in a CMOS semiconductor integrated circuit, a clock signal, a clock enable signal, data inputs, an address signal, and a command input from an external system must be input to input buffers of a semiconductor integrated circuit to be converted to a CMOS voltage level. Conventional input buffers include a clock buffer, a clock enable buffer, a data buffer, and an address buffer. The operational timing of the clock buffer, the clock enable buffer, the data buffer, and the address buffer are illustrated in FIG. 1.
Referring to FIG. 1, it can be seen that a clock buffer receives and buffers a clock signal and is always turned on excluding the case where the clock buffer performs a self-refresh operation. In the case of a self-refresh operation, the clock buffer is not controlled by an external command but performs active and precharging operations at a predetermined interval using an internal counter, during which the clock buffer is not driven.
A clock enable buffer buffers the clock enable signal, except for in a power-down mode, and is always turned on.
An address buffer receives the address signal and is always turned on excluding the case where the address buffer is in the power-down mode. The address buffer is turned off in the power-down mode since the address is not received from an external circuit during power down mode.
The data buffer buffers a data signal, is turned on during a write operation, and is turned off in the other operation modes. This is because the data signal is only received when a write operation is performed.
In a double data rate synchronous dynamic random access memory (DDR SDRAM), a write latency exists. Accordingly, the data buffer is turned on in the write operation. However, the write latency does not exist in a single data rate synchronous dynamic random access memory (SDR SDRAM), where the data must be immediately received when a write command is received, and therefore the data buffer must be driven before the write operation. Accordingly, in the case of the SDR SDRAM, the data buffer is turned on in all modes, except the read and precharge modes.
In conventional semiconductor integrated circuits, the same source power Int_v (hereinafter, referred to as a power supply voltage) is provided to the clock buffer, the clock enable buffer, the address buffer, and the data buffer. The power supply voltage Int_v is a buffer-exclusive power source obtained by down-converting an external voltage into an internal power voltage through a common internal voltage generating circuit. As described above, the input buffers are turned on and off at various, differing times. This is done in part to reduce unnecessary power consumption.
FIG. 2 is a diagram, illustrating a conventional semiconductor integrated circuit that includes a power supply voltage generating block and an input buffer block. The power supply voltage generating block includes an active driver 10 and a standby driver 20.
The active driver 10 is turned on in an active mode and is turned off in the precharge mode as well as in the power-down mode.
The standby driver 20 is always driven regardless of operation modes. That is, since the standby driver 20 must continuously provide the power supply voltage Int_v to the input buffers, the standby driver 20 must always be on. On the other hand, the active driver 10 is driven only in the active mode to additionally supply the power supply voltage Int_v to the input buffers to compensate for any insufficient supply of power caused by current consumption during the active mode.
The input buffers include the clock buffer 30, the clock enable buffer 40, the address buffer 50, and the data buffer 60. The input buffers receive the power supply voltage Int_v from the active driver 10 and the standby driver 20 and use it to buffer signals input to the input buffers.
The data buffer 60 is turned on only during a write operation and the other input buffers are always turned on excluding the case where they are in the power-down mode. Therefore, since the timing of operation of the data buffer 60 is different from that of the other input buffers, the operation timing interval in which the current consumption is generated by the power source of the data buffer 60 is different from the operation timing interval in which the current consumption is generated by the power sources of the other input buffers.
In addition, in a conventional layout, the input buffers are arranged by kind in various regions of the layout. Accordingly, different types of buffers can be located in separate regions, e.g., the data buffer and the address buffer, or the data buffer and the clock buffer, may be arranged in different regions that are separated from each other by a predetermined distance. Therefore, in order to supply the power supply voltage Int_v to the different input buffers, the length of a power line for transmitting the power supply voltage Int_v can increase for certain buffers relative to certain other buffers.
The increased length will increase the capacitance and resistance of the power line, which means that the supply of power to an input buffer farther away from the power supply voltage Int_v may be delayed and the voltage supplied may be reduced. In addition, the efficiency of the current supply to an associated power supply voltage driver may deteriorate in accordance with the position of each input buffer. That is, in order to ensure an effective current supply for each buffer, it is necessary that a power supply voltage driver be additionally provided in each region where each buffer is positioned.
Furthermore, although the data buffer 60 operates only in the write operation, when the data buffer is driven, the active driver and the standby driver are both driven during other operational modes. Thus, e.g., the active driver is also driven when the data buffer is not driven. Therefore, the operational current of the active driver 10 is greater than that of the standby driver. When the external supply voltage VDD increases, the operational current can reach several mA, which can result in excessive current consumption.